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At the ongoing "ISSCC 2016" (January 31–February 4, 2016, San Francisco, USA), several papers on 3D (three-dimensional) laminated CMOS image sensors were presented. Within "SESSION6 Image Sensors," which featured nine presentations, three of them focused on 3D stacking techniques for CMOS image sensors. Historically, the industry has explored 3D integration, but challenges like high costs and low power efficiency have made it difficult to scale. However, recent advancements have enabled more modular approaches to 3D design.
One notable presentation was from TSMC titled “A 1.5V 33Mpixel 3D-Stacked CMOS Image Sensor with Negative Substrate Bias†(Paper 6.8). The talk highlighted a key challenge: when stacking an image sensor chip with an image processing circuit, there's a voltage mismatch. As circuits become smaller, the processing chip operates at around 1V, while the sensor requires about 2V. To address this, TSMC introduced a negative bias on the sensor’s substrate. This approach helps balance the voltage difference without compromising performance.
The company also emphasized its modular technology, allowing for flexible pixel count adjustments. By combining approximately 8.3 megapixel 4K image sensors into a single tile-like module, they can increase resolution without major redesigns. This is achieved by stacking the image processing circuit directly on top of the sensor, rather than using traditional 2D layouts. Additionally, TSMC improved the image sensor chip size by integrating rewiring layers that facilitate pixel access.
During the lamination process, the wiring layer of the image sensor chip is bonded to the wiring layer of the processing chip using a back-side illumination (BSI) type CMOS sensor. Notably, TSV (through-silicon via) technology was not used; instead, adhesion was employed for electrical bonding and insulation. TSMC aims to expand the market for image sensors by showcasing their capability to support diverse applications.
Another presentation came from Toshiba, titled “A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple-Sampling PGA†(Paper 6.7). This paper discussed a new read circuit design that uses a low-power amplifier and ADC. Although Toshiba did not disclose business plans, the focus was on reducing power consumption and improving signal quality. This approach could be beneficial for smartphone cameras and other mobile devices.
Additionally, NHK Broadcasting Technology Research Institute, Brookman Technology, TSMC, and Shizuoka University presented a paper titled “A 1.1μm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters†(Paper 6.9). They showcased how to make image sensors smaller and more energy-efficient for 8K TV content. Like TSMC, they used BSI sensors and avoided TSV technology, opting instead for direct bonding between the sensor and processing chip.
In this design, signals from 1.1μm pitch pixels are connected to the lower-layer processing chip in 4×4 pixel groups. The ADC in the read circuit was reconfigured into a three-stage system, using cyclic stages for speed and successive approximation for accuracy. While the paper reported achieving 8 frames at 240fps, the data was optimized for publication. The NHK Institute noted that practical use of 8K cameras based on this standard is still under consideration.
Finally, Matsushita delivered three presentations, two of which focused on organic film-based image sensors. These emerging technologies show promise for future imaging solutions, particularly in flexible and low-cost applications. Overall, ISSCC 2016 provided a comprehensive look at the latest developments in 3D-stacked CMOS image sensors, highlighting both technical innovations and real-world applications.