Cable Box,Junction Boxes,Cable Connection Box,Waterproof Cable Box,Electrical Junction Boxes Jiangmen Krealux Electrical Appliances Co.,Ltd. , https://www.krealux-online.com
At the ongoing "ISSCC 2016" (January 31–February 4, 2016, San Francisco, USA), several papers on 3D (three-dimensional) laminated CMOS image sensors were presented. Within the "SESSION 6: Image Sensors" forum, which featured nine presentations, three of them focused specifically on 3D integration in CMOS image sensors. Historically, the industry has been exploring ways to achieve 3D stacking, but challenges such as higher costs and power consumption have limited widespread adoption. However, recent advancements have made it easier to modularize 3D designs.
One notable presentation came from TSMC, titled "A 1.5V 33Mpixel 3D-Stacked CMOS Image Sensor with Negative Substrate Bias" (Paper 6.8). The talk discussed how TSMC is addressing voltage mismatches between the image sensor chip and the image processing circuit chip. As devices become smaller, the image processing circuit operates at lower voltages—around 1V—while the image sensor still requires about 2V. To resolve this, TSMC introduced a negative bias on the image sensor’s substrate, enabling better compatibility between the two chips.
The company also showcased its modular technology, which allows for flexible pixel count adjustments by combining multiple 8.3 megapixel 4K image sensors into a single module. This approach simplifies scaling without requiring major design changes. The image processing circuit is stacked directly on top of the image sensor, rather than being placed side by side. Additionally, TSMC improved the image sensor’s size by incorporating a rewiring layer that facilitates connections to each pixel.
During the lamination process, TSMC used back-side illumination (BSI) type CMOS sensors, bonding the wiring layers of both chips through adhesion instead of using costly through-silicon vias (TSVs). This method ensures electrical connectivity and insulation. TSMC sees this as a key opportunity to demonstrate its technological readiness for diverse applications, aiming to expand the market for image sensors.
Another presentation by Toshiba, titled "A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple-Sampling PGA" (Paper 6.7), highlighted a new low-power read circuit and ADC design. Though Toshiba did not provide specific business details, the technology aims to reduce power consumption while improving performance, making it suitable for smartphone and other mobile applications.
Additionally, NHK Broadcasting Technology Research Institute, Brookman Technology, TSMC, and Shizuoka University presented a paper on a 1.1μm 33Mpixel 240fps 3D-stacked CMOS image sensor with a 3-stage cyclic-based ADC (Paper 6.9). The presentation discussed how NHK is working on compact, low-power image sensors for 8K TV content. Like TSMC, they avoided using TSVs and instead bonded BSI image sensors with image processing chips. The design uses a 4x4 pixel grouping to connect signals to the lower-layer wiring, and the ADC employs a hybrid configuration—cyclic for the first two stages and successive approximation for the third—to balance speed and power efficiency.
Although the paper mentioned achieving 8K video at 240fps, the data was optimized for publication. NHK stated that practical use of 8K cameras based on this standard is still under consideration.
Finally, Matsushita delivered three presentations, with two focusing on organic film-based image sensors. These developments reflect the growing interest in alternative materials and structures to enhance image sensor performance and flexibility. Overall, the ISSCC 2016 conference highlighted significant progress in 3D CMOS image sensor technology, emphasizing modularity, power efficiency, and scalability.