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The main pins of an FPGA typically include user I/O, configuration pins, power supply pins, clock pins, and special application pins. Some of these pins are multipurpose, so it's essential to consult the specific FPGA datasheet before designing the circuit to ensure proper usage and avoid conflicts.
Let’s take the Cyclone series from Altera as an example to explore the various pin functions in an FPGA.
(1) User I/O
User I/O pins (often labeled as I/Onum or LVDSnumn) can function as input, output, or bidirectional ports. They can also serve as the negative terminal of an LVDS differential pair. When creating a schematic for an FPGA, it's common to group similar pins into blocks for clarity. For instance, Figure 2.3 shows a typical schematic layout of user I/O pins.
(2) Configuration Pins
These pins are crucial for initializing and programming the FPGA. Key configuration pins include:
- MSEL[1..0]: Selects the configuration mode (e.g., active, passive, serial, parallel).
- DATA0: Serial data input from the configuration device.
- DCLK: Serial clock output used by the configuration device.
- nCSO: Chip select output, connected to the configuration device.
- ASDO: Serial data output, connected to the configuration device.
- nCEO: Enables the next device in a chain after configuration is complete.
- nCE: Input enable signal for the download chain.
- nCONFIG: Starts the configuration process.
- nSTATUS: Indicates the status of the configuration.
- CONF_DONE: Signals that configuration is complete.
Figure 2.4 illustrates the configuration pin schematic.
(3) Power Supply Pins
FPGAs require several voltage supplies to operate correctly:
- VCCINT: Core voltage, usually around 1.2V–1.5V depending on the manufacturing process.
- VCCIO: I/O voltage, commonly 3.3V but may support other voltages like 1.8V or 5V.
- VREF: Reference voltage for I/O standards.
- GND: Ground connection for the circuit.
(4) Clock Pins
Clock-related pins manage the timing and synchronization of the FPGA:
- VCC_PLL: Voltage for the phase-locked loop (PLL).
- VCCA_PLL: Analog power for the PLL.
- GNDA_PLL and GNDD_PLL: Ground connections for analog and digital parts of the PLL.
- CLKnum (LVDSCLKnump/n): Clock input for the PLL, supporting LVDS signals.
- PLLnum_OUTp/n: Clock output from the PLL, also supporting LVDS.
Figure 2.6 shows the clock pin schematic.
(5) Special Purpose Pins
Some pins have unique functions:
- VCCPD: Controls the drive voltage for certain I/Os.
- VCCSEL: Manages the input buffer voltage for configuration and PLL.
- PORSEL: Configures power-on reset behavior.
- NIOPULLUP: Enables or disables internal pull-up resistors on I/Os during configuration.
- TEMPDIODEn/p: Connects to temperature-sensitive diodes for thermal monitoring.
In addition, some pins are global clocks, which are critical for high-speed designs and should be routed carefully for optimal performance. Understanding these pin functions is vital for successful FPGA design and implementation. Always refer to the manufacturer’s documentation for detailed specifications and recommendations.