Performance and power/area are often conflicting design goals, like “yin” and “yang” in SoC design. Each generation of SoCs must constantly struggle between these two design goals, and when you feel that you are finally achieving the perfect balance, the new design goals will drive you to move forward!

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In fact, the rapid advancement of SoC performance goals is truly amazing. Yesterday's "advanced" performance, in a blink of an eye, has become "intermediate" today.

Taking smartphones as an example, with the rapid spread, an emerging but fast-growing entry-level smartphone market has taken shape. These phones, which are less than $100, do not have the full functionality of high-end products, but still require a certain level of performance to support more common features. A number of early-market low-cost smartphones use single-core processors, but newer phones will use multi-core designs, possibly for application processing and baseband processing, or a combination of the two. Therefore, we need an excellent mid-range multi-core processor. Considering the massive characteristics of mobile products, low cost and low power consumption are also very important design goals.

Entry-level smartphones are a model for "yin and yang" applications, but they are not the only devices that demand area and power efficiency, and many other devices require such mid-range multicore processing. Driven by broadband, mobile and new applications, SoCs for products such as SSD controllers, home gateways and in-vehicle infotainment systems are increasingly demanding performance for multicore applications. While these applications do not necessarily require the highest performance levels, they still require good mid-level performance. Moreover, achieving a balance of power and performance under strict design constraints is more challenging than just requiring high performance design.

We are pleased to introduce the new MIPS interAptiv multi-threaded, multi-core processor family, which provides the high-end mid-core multi-core performance required for a wide range of embedded devices, while offering low power and low cost features. Ideal for products with similar needs. The efficiency of the interAptiv kernel is primarily due to the use of multi-threading technology, which is particularly valuable for applications with high parallelism and pipeline stalls due to memory access. In terms of unit area and unit power consumption, the interAptiv core achieves the highest performance level, which is more advantageous than the core of the same level. Multicore support from interAptiv means you have a platform that is extremely scalable and efficient.

Compared with MIPS' previous generation multi-threaded kernel, the interAptiv kernel mainly enhances multi-core performance. As mentioned earlier, more and more mid-range designs are also transferred to multiple cores, so suddenly, the modules connecting these cores can provide Good performance becomes very important. The interAptiv core uses the MIPS second generation synchronization manager (CM) that integrates the L2 cache controller. By integrating L2 cache controllers and other enhancements, CM can significantly improve latency and provide optimal system processing power.

The interAptiv core also enhances power management features, intelligently selects the L1 ICACHE path, and has 32-bit access to L1 DCACHE and DSPRAM, as well as the ability to turn off the kernel clock based on bus requirements. In addition to these enhancements, the power management features of our previous generation of multi-threaded/multi-core products, including single-core based voltage gates and clock-gated cluster power control, are included in the interAptiv core.

For designers developing SoCs for high-reliability applications, the interAptiv core provides ECC error correction for L1 DCACHE and DSPRAM memory, making it ideal for applications requiring data integrity, such as storage or automotive driver assistance systems.

Therefore, although we can't completely eliminate the effort to balance the performance and power/cost efficiency, (sorry, there is no button to solve this problem), but through the interAptiv kernel, we can design the entire design. The process has become easier. Want to know how to use the interAptiv kernel to achieve a balance between "yin and yang"?

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